Integrated circuits are made up of millions of active devices formed in or on a semiconductor substrate, such as a silicon wafer. The active devices are chemically and physically connected to the semiconductor substrate. Different layers of the active devices are interconnected through the use of vias to form functional circuits. Typical layers of a semiconductor substrate comprise a first metal layer, an interlevel dielectric layer (ILD), and sometimes a second metal layer. Additional layers on a semiconductor substrate can be formed separately and serially. The vias between each layer are filled with metal to complete a circuit spanning more than one layer. Interlevel dielectrics, such as doped and undoped silicon dioxide (SiO2) and/or low-κ dielectrics, are used to electrically isolate the different metal layers.
There are several different methods to form active devices on an ILD. In the single damascene process, a circuit design is first patterned onto the ILD. The patterned ILD comprises a series of trenches mirroring the circuit design. Then a metal film is plated over the entire patterned ILD surface to fill in the trenches which reflect the patterned circuit design. In the dual damascene process, the vias and the patterned circuit design are formed on the ILD at the same time. The resulting patterned ILD surface of vias and trenches is filled when a metal film is plated over the entire ILD.
When metal deposition is by electroplating or by an electroless process, the plating may be preceded by the deposition of a plating base or seedlayer over the entire surface of the patterned ILD. The plating base or seedlayer can be deposited by, for example, chemical vapor deposition. Various metals and alloys, such as, for example, titanium (Ti), titanium nitride (TiN), aluminum copper. (Al—Cu), aluminum silicon (Al—Si), copper (Cu), tungsten (W), platinum (Pt), ruthenium (Ru), iridium (Ir), and combinations thereof can be used to deposit a plating base or seedlayer onto the vias and trenches.
Also, barrier layers that may improve adhesion and/or prevent metal/insulator interactions or interdiffusion may be deposited between the plating base or seedlayer and the ILD. The barrier layer may be titanium (Ti), titanium nitride (TiN), titanium alloy, tantalum (Ta), tantalum nitride (TaN), tantalum alloy, tungsten (W), tungsten nitride (WN), or tungsten alloy.
Electroless plating and electroplating of Cu and Cu alloys offer the prospect of low cost, high throughput, high quality plated films and efficient via and trench filling capabilities. Electroless plating generally involves the controlled autocatalytic deposition of a continuous metal film on the semiconductor substrate surface by the interaction in solution of a metal salt and a chemical reducing agent. Electroplating comprises the electro deposition of an adherent metallic coating on an electrode employing externally supplied electrons to reduce metal ions in a plating solution. A seed layer is required to catalyze electroless deposition or to carry electrical current for electroplating. For electroplating, the seed layer must be continuous. For electroless plating, very thin catalytic layers, e.g., less than 100 Å, can be employed in the form of islets of catalytic metal.
During the plating of metal into the trenches and vias, the narrower features become filled before their wider counterparts. For example, all features with widths less than 2 microns will be filled before those with widths greater than 5 microns. Hence, to fill trenches or vias with widths of 50 microns, the smaller trenches and vias, typically with widths less than 5 microns, are overplated. This is known in the art as metal overburden.
Once the plating of metal has been completed, the substrate surface is planarized by CMP to remove metal overburden and isolate and define the wiring pattern. CMP is becoming a more important process in the manufacture of semiconductor surfaces because more active devices are being packed into smaller areas in semiconductor substrates and because unconventional metals, such as copper, are being used in order to improve the over-all performance of the circuits. More active devices in a given area on a semiconductor substrate require better planarization techniques due to the unevenness of the topography formed by the features themselves, such as metal lines, or of the topography of the layers formed over the features. Because many layers of metals and ILDs are formed successively one on top of another, each layer needs to be planarized to a high degree if higher resolution lithographic processes are to be used to form smaller and a higher number of features on a layer in a semiconductor substrate.
CMP combines a chemical treatment of a surface layer with a mechanical removal of the chemically treated layer. Typical CMP systems contain an abrasive material, such as silica or alumina, suspended in an oxidizing, aqueous medium, which is applied to a substrate between the substrate and a polishing pad that is moved relative to the substrate to effect the polishing of the substrate.
The mechanical kinetics of CMP for a blanket deposited metal into trenches or vias in an ILD is explained by the Preston equation given by:(ΔH/Δt)=Kp(L/A)(Δs/Δt), where(ΔH/Δt) is the removal rate of the material in terms of change in height per unit time of polishing, and L is the load imposed over a surface area, A. (Δs/Δt) is the relative velocity of the pad to the substrate, and Kp is Preston's coefficient. The equation predicts that, for a given (L/A), the weight loss of the polished material is proportional to the amount of travel, and it remains invariant with time. The polishing rate increases with the pressure (L/A) and velocity. In other words, the removal rate is a linear function of pressure, so that high points are polished more rapidly, and the surface quickly becomes planar.
A CMP system ideally results in a polished planar surface without residual metal films on the polished surface of the ILD, and with all of the trenches having metal at heights that are even with the level of the polished surface of the ILD. However, once the high points are quickly polished, the load is shared by lower points which are now within reach of the pad, thereby resulting in a relatively lower polishing pressure. After total removal of the metal layer from the surface of ILD, the polishing is shared between the metal layer that is level with the ILD surface and the ILD itself. Since the polishing rate of the metal is different from that of the ILD, and, in the case of copper, faster than that of the ILD, metal is removed from further below the level of the ILD, thus leaving spaces. The formation of these spaces is known in the art as dishing. This dishing in turn causes a higher pressure being built up at the edges of the trench/via openings, and therefore, erosion of the ILD edge and/or further dishing of the metal as the material of the polishing pad is subjected to elastic deformation by the ILD edge.
Severe dishing and ILD erosion in large metal features is a source of yield loss, especially when they occur at lower levels of the device, where they cause trapped metal defects in the above lying layer(s). The longer time needed to remove the thicker metal overburden on the narrowest metal trenches and vias is one of the main culprits responsible for the low throughput and yield loss in the CMP process.
Consequently, there remains a need for a method of polishing a substrate comprising a metal layer without significant dishing defects through a use of a CMP process. The invention provides such a method. These and other characteristics and advantages of the invention will be apparent from the description of the invention provided herein.